1. Field of the Invention
The present invention relates to a polycrystalline thin film transistor liquid crystal display device, and more particularly, to an apparatus for applying an OFF-state stress to a p-type polycrystalline thin film transistor for stabilization.
2. Discussion of the Related Art
Until recently, cathode-ray tubes (CRTs) have generally been used for display systems. However, use of flat panel displays is becoming increasingly common because of their small depth, low weight, and low power consumption. Presently, thin-film transistor-liquid crystal displays (TFT-LCDs) are being developed that have high resolution, small depth and high color reproducibility.
When a pixel is turned on by a switching element, the pixel transmits light from a backlight unit. Amorphous silicon (a-Si:H) thin film transistors (TFT) that include a semiconductor layer of amorphous silicon are widely used as switching elements because the amorphous silicon thin film can be formed on a large-sized insulating substrate such as a glass substrate under a low temperature. However, even though TFT-LCDs using amorphous silicon TFTs have an advantage over CRTs of low power consumption, the price of TFT-LCDs is higher than that of CRTs because TFT-LCDs require an expensive driving circuit.
FIG. 1 is a schematic plane view of an amorphous silicon thin film transistor liquid crystal display device according to the related art.
In FIG. 1, a substrate 10 includes a display region “D.” A gate driving integrated circuit (IC) 20 and a data driving IC 30 are formed between the display region “D” and a printed circuit board (PCB) 40. Generally, the gate and data driving ICs 20 and 30, which are referred to as a large scale integration (LSI), are fabricated by using single crystalline silicon and connected to the substrate by a tape automated bonding (TAB) method. However, as the resolution of the liquid crystal display (LCD) device increases, more leads are necessary to connect the substrate and the driving LSI. For example, in a super extended graphic array (SXGA) display having 1280×1024×3 pixels, at least 1280×3×1024 leads are required for connection. The process for fabricating large numbers of leads is complex, thereby reducing reliability and production yield. Moreover, the price of LCD devices increases due to the expensive driving LSI. To solve these problems, LCD devices using a polycrystalline silicon thin film transistor are suggested.
FIG. 2 is a schematic plane view of a polycrystalline silicon thin film transistor liquid crystal display device according to the related art.
In FIG. 2, a substrate 10 includes a display region “D.” Contrary to LCD devices using an amorphous silicon thin film transistor, a gate driving circuit 22 and a data driving circuit 32 of the LCD device of FIG. 2 are directly formed on the substrate 10 using a polycrystalline silicon as a switching element of each pixel (not shown). Accordingly, an additional process of connecting the substrate and a driving LSI is not necessary.
FIG. 3 is a schematic cross-sectional view of a polycrystalline silicon thin film transistor according to the related art.
In FIG. 3, a first insulating layer (a buffer layer) 40 is formed on a substrate 10 and an active layer 42 of polycrystalline silicon is formed on the first insulating layer 40. A second insulating layer (a gate insulating layer) 44 is formed on the active layer 42 and a gate electrode 46 is formed on the second insulating layer 44 over the active layer 42. A third insulating layer (an interlayer insulating layer) 48 having contact holes is formed on the gate electrode 46. Source and drain electrodes 50a and 50b are formed on the third insulating layer 48 and connected to the active layer 46 through the contact holes. A fourth insulating layer (a passivation layer) 52 is formed on the source and drain electrodes 50a and 50b. A pixel electrode 54 is formed on the fourth insulating layer 52 and connected to the drain electrode 50b. 
FIG. 4 is a schematic perspective view of a liquid crystal display device according to the related art.
In FIG. 4, first and second substrates face into and are spaced apart from each other, and a liquid crystal layer is interposed therebetween. The first substrate having a thin film transistor (TFT) “T” and array lines, and the second substrate having a black matrix and a color filter layer are fabricated through various process steps. Among the various process steps, a process for stabilizing the TFT “T” may be performed for the first substrate having the TFT “T” or for the attached first and second substrates, i.e. for a cell having the TFT “T.”
When a polycrystalline silicon (p-Si) TFT-LCD device is driven for a long period of time under room temperature, carriers generated at a P-N (positive-negative) junction of the p-Si TFT produce an OFF-current (IOFF) may leave residual images on the LCD device panel which can degrade the LCD device. Accordingly, a stabilizing process is performed in which an OFF-state stress is applied to the P-type TFT to prevent the residual images. To apply an OFF-state stress means to apply a voltage opposite to or different from a normal voltage. Through this stabilizing process, the OFF-current may be reduced and a mobility of the TFT may be improved.
FIG. 5 is a schematic circuit diagram illustrating one pixel of a liquid crystal display device according to the related art.
In FIG. 5, a P-type thin film transistor (P-TFT) is formed in each pixel region. A gate electrode and a source electrode of the P-TFT are connected to a gate line 12 and a data line 14, respectively. A drain electrode of the P-TFT is connected to a storage capacitor “CST” and a liquid crystal capacitor “CLC.” The storage capacitor “CST” is connected to a common line 16, and the liquid crystal capacitor “CLC” is connected to the common electrode 18.
FIGS. 6A and 6B are a schematic circuit diagram and a timing chart, respectively, illustrating a stabilizing method including a first OFF-state stress applied to a liquid crystal display device according to the related art.
In FIGS. 6A and 6B, when a low gate voltage (for example, −10V) is applied to a gate electrode of a P-TFT through a gate line 12, the P-TFT is turned ON. Since a low data voltage (for example, −10V) is applied to a source electrode of the P-TFT through a data line 14, the low data voltage is also applied to a drain electrode of the P-TFT. After the low data voltage is applied to the drain electrode of the P-TFT, a high gate voltage (for example, 30V) is applied to the gate electrode of the P-TFT, thereby turning OFF the P-TFT. Then, a high data voltage (for example, 0V) is applied to the source electrode of the P-TFT. Since the drain electrode maintains the low data voltage and the P-TFT maintains a turn-OFF state, a first OFF-state stress including the high gate voltage of the gate electrode, the high data voltage of the source electrode and the low data voltage of the drain electrode is obtained as a forward bias mode.
FIG. 6C is a schematic cross-sectional view illustrating an effect of a first OFF-state stress of a stabilizing method according to the related art.
In FIG. 6C, since a voltage difference (for example, 40V) between a gate electrode and a drain electrode is higher than that between the gate electrode and a source electrode, an electric field between the gate electrode and the drain electrode is higher and becomes dominant. Accordingly, electrons adjacent to the drain electrode are accelerated by the electric field and captured by an interface of a polycrystalline silicon layer and a trap in the polycrystalline silicon grain boundary. The captured electrons cure the interface and the trap of the polycrystalline silicon layer adjacent to the drain electrode.
FIG. 6D is a current-voltage (I-V) curve illustrating an OFF-current of a P-TFT after a first OFF-state stress of a stabilizing method according to the related art.
In FIG. 6D, an OFF-current of a P-TFT is improved after a first OFF-state stress is applied to the P-TFT because defects of the P-TFT are cured.
FIGS. 7A and 7B are a schematic circuit diagram and a timing chart illustrating a stabilizing method including a second OFF-state stress applied to a liquid crystal display device according to the related art, respectively.
In FIGS. 7A and 7B, when a low gate voltage (for example, −10V) is applied to a gate electrode of a P-TFT through a gate line 12, the P-TFT is turned ON. Since a high data voltage (for example, 0V) is applied to a source electrode of the P-TFT through a data line 14, the high data voltage is also applied to a drain electrode of the P-TFT. After the high data voltage is applied to the drain electrode of the P-TFT, a high gate voltage (for example, 30V) is applied to the gate electrode of the P-TFT, thereby turning OFF the P-TFT. Then, a low data voltage (for example, −10V) is applied to the source electrode of the P-TFT. Since the drain electrode maintains the high data voltage and the P-TFT maintains a turn-OFF state, a second OFF-state stress including the high gate voltage of the gate electrode, the low data voltage of the source electrode and the high data voltage of the drain electrode is obtained as a reverse bias mode.
FIG. 7C is a schematic cross-sectional view illustrating an effect of a second OFF-state stress of a stabilizing method according to the related art.
In FIG. 7C, since a voltage difference (for example, 40V) between a gate electrode and a source electrode is higher than that between the gate electrode and a drain electrode, an electric field between the gate electrode and the source electrode is higher and becomes dominant. Accordingly, electrons adjacent to the source electrode are accelerated by the electric field and captured by an interface of a polycrystalline silicon layer and a trap in the polycrystalline silicon grain boundary. The captured electrons cure the interface and the trap of the polycrystalline silicon layer adjacent to the source electrode.
FIG. 7D is a current-voltage (I-V) curve illustrating an OFF-current of a P-TFT after a second OFF-state stress of a stabilizing method according to the related art.
In FIG. 7D, an OFF-current of a P-TFT is improved after a second OFF-state stress is applied to the P-TFT because defects of the P-TFT are cured. Moreover, an ON-current is also improved.
In a stabilizing method including an OFF-state stress, a gate voltage having two values and a data voltage having two values are used to improve a P-TFT property by reducing an OFF-current. However, since forward and reverse modes are alternated, the stabilizing method is complex. Moreover, when many LCD cells are fabricated in one substrate, the stabilizing method is performed for each LCD cell. Accordingly, it takes much time to perform the stabilizing method, thereby reducing production yield.